Research & Funded Projects:

1- Trading Power, Performance and for Energy-Harvested Implatable Medical Devices

Students: Ehsan Aerabi, Milad Bohlouli
2016 - 2019
Embedded PBTIroducts

Implantable Medical Devices (IMD) are a category of embedded systems which are placed in a human body to facilitate monitoring and treating chronic diseases. In recent years, IMDs have been equipped with wireless communication which can provide diagnosis data to physicians and receive command and updates from them. This opens the doors for remote attackers. Hence, we need to provide confidentiality and authenticity for the device and the physician's data and commands. To achieve this, we need an extra source of energy for cryptographic algorithms and protocols to involve. Recent research suggest energy harvesting from internal body resources like body movements and blood glucose. This type of energy provides independent power for the IMDs which can send realtime data to/from physician's device. But this source is not a reliable and constant. In this research we try to design a secure communication framework which can utilize the existing harvested energy to achieve the maximum security and throughput. It can reconfigure itself to cope with the limited energy by changing the security and performance parameters. Finding an optimum solution requires a design space exploration among all the apstraction layers in an embedded systems design starting from hardware and architecture to the algorithms and protocols.

2- Reliable VLSI Circuits and Systems Design

Students: Masoud Katirae, Dadi
2015 - 2019

Downscaling of VLSI Circuits into the nanometer regime has brought major reliability challenges. Reduction of threshold voltage, supply voltage and internal node capacitances due to shrinking of feature size, ever increasing of complexity, and operating frequency are the main cause of the reliability issues in Nano-scale technologies. Radiation induced faults, the so called soft errors, are one of the serious reliability threat in nanometer digital circuits. Two reasons make the soft error becoming a major threat to reliability of nanometer digital systems: (1) nodal capacitance is down-scaled and the charge of the capacitance can be affected even with low energetic particles. (2) An energetic particle can affect two or more physical adjacent nodes in the layout and causes multiple faults. To protect a VLSI circuit against soft error, two steps are required including: 1) soft error rate estimation to identify the most vulnerable components; 2) soft error protection of must vulnerable components considering other design objectives like power consumption and performance.
Several methods have been proposed to estimate the soft error rate of digital circuits in recent years. The straight forward method to estimate the soft error rate is Monte Carlo simulation based fault injection. Although, very precise results can be achieved, the execution times of such simulations are intractable for large scale circuits. To address this issue, Statistical Static Timing Analysis (SSTA) based methods have been proposed. These methods are very fast and mostly have comparable accuracy to fault injection methods. However, emerging reliability threats including: (a) The single particle strike and multiple transient faults (b) Process Variations (c) aging effects have remarkably reduced the accuracy and even applicability of previously proposed SSTA based methods. The aging and PV impact on gate delay model and affect timing masking and logical masking mechanisms. In recent years, some research work has been devoted to taking into account the effects of PV and aging separately, however, the joint consideration of both should be performed to have an accurate SER estimation.
In addition to soft errors, as mentioned above, aging effects and process variations are the emerging and important reliability threats in Nano-scale VLSI technologies. There are some various sources of aging induced MOS parameters variations, such as negative and positive Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Time Dependent Dielectric Breakdown (TDDB). However, among these sources, the BTI has become the major reliability issues in nanometer MOS devices. Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors cause a threshold voltage shift (∆V_th) when they are in the stress phase (ON-State), at elevated temperatures. When PMOS transistor is negatively biased (stress phase) i.e. V_GS=-V_DD, the interaction between the inversion layer holes and the hydrogen-passivated interface Si atoms breaks the Si-H bonds along the substrate-oxide interface. The H atoms can combine to form H_2 molecules and diffuse away (through oxide), then interface traps are generated. These donor-like traps can capture holes and generate bulk oxide traps, giving rise a net positive charge in the gate oxide. The end result is a shift in the threshold voltage of PMOS transistor. By removing the biased voltage, the hydrogens near the interface diffuse back and anneal dangling bands which reduces the number of interface traps and mitigates the NBTI effect (recovery phase). However, this cannot eliminate all the traps, and in long term the threshold voltage increases which in turn results in gate delay increase. Briefly, in presence of NBTI, the delay of a gate increases as it ages. A similar mechanism can be described for NMOS transistors as well (PBTI). In technology size above 90nm, NBTI in PMOS transistors was more significant than PBTI in NMOS transistors and the PBTI was considered to have a negligible effect, however, due to use of high-k dielectrics to reduce gate leakage, PBTI effects have become comparable to NBTI effects.
The PMOS/NMOS I-V characteristics are function of transistor parameters like initial threshold voltage (V_th0), effective oxide thickness (EOT), effective width (W_eff) and effective length (L_eff). In nanometer CMOS technology, precise control of critical dimensions and the other parameters such as channel doping density is very difficult. This results in a large variation in transistor parameters within and across dies. These variations are a consequence of random dopant fluctuations (RDFs) and photolithographic process deviations such as line edge roughness (LER). In particular, variations in Channel doping density, oxide thickness, channel width and length significantly impact on transistor characteristics and accordingly circuit performance. Process variations and aging effects impact on the timing behavior of circuits, as the delay of a CMOS gate is not a deterministic parameter and increases with time. In fact, a gate delay is firstly not a constant value and increases over time due to aging effects, secondly, it is a statistical parameter due to PVs. In fact, the gate delay is a time-dependent and fabrication-dependent parameter due to BTI and PV. As a result, process variation and aging effects should take into account in circuit timing analysis. In this research project, we intend to design a Gate-Level soft error rate estimation methodology based on Statistical Static Timing Analysis considering the effects of process variations and ageing.

3- Secured & Energy Efficient health-care solutions for IoT Market

People involved: Zahra Kazemi, Athanasios Papadimitriou, David Hely and M. Fazeli
2017 - 2020

Health care systems and treatment approaches adopted in hospitals are greatly evolving due to the introduction of IoT medical devices. This leads to high quality, accurate, efficient and personalized treatment services. Most of this kind of IoT devices consist of a Micro-Controller Unit (MCU), various sensors, actuators and a communication network. Infusion pumps are one popular application of IoT devices in healthcare systems. Their main task is to deliver medicine to a patient in a controlled and remote manner. In general, the advantages of such infusion pumps are the simplicity of medicine administration, the capability of delivering precise doses as well as remote monitoring by specialists. For example, automatic insulin infusion pumps can be used at homes or clinics to deliver insulin. Such connected infusion pumps, used to deliver medicine to patients remotely, have been the target of attackers. This example shows that broad adoption of IoT medical devices imposes the need for safe functionality as well as data security and confidentiality. In this project, we specify a dedicated hardware threat evaluation platform for MCU-based connected device software developers. The main purpose of such a platform is to provide a tool to software developers, in order to easily evaluate the robustness of their system against hardware-based threats. Software developers embed within the application, mechanisms in order to cipher data to be exchanged, as well as conditional execution to check access right and so on. The main issue is that such security operations may be completely canceled if they are not secure against hardware attacks. Embedded software developers cannot keep a current understanding of hardware security vulnerabilities and relevant attack methods to examine the device from all sides. Therefore, it is not possible for them to evaluate the robustness of their designs against such attacks. To enable evaluation against hardware threats by developers which are not hardware security experts there is the need for relevant evaluation tools and platforms an evaluation platform should target ease of use by non-hardware security specialists.

4- Design of Efficient Non-Volatile Logic Circuits

People involved: Vahid Jamshidi, Sadjad Aghadadi, Mahdi Fazeli
2014 - 2018

Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). Some disadvantages of this technology include: long reboot latency of programmable circuits, data loss during unexpected power supply interruptions and high leakage currents, especially when the technology scales to 100 nm and below. In order to improve the reboot speed, data security and reduce energy dissipation, recently, the design and implementation of circuits using nano-scale magnetic cells is highly regarded. Nano-scale magnetic cells such as MTJs (Magnetic Tunnel Junction) are tiny, fast, programmable, non-volatile, and compatible with semi-conductor elements. They also dissipate zero static power and can be rearranged. These special features have made MTJs a possible substitute for future logic devices and memories. Accordingly, by considering nano-scale magnetic cells as an effective substance for the reduction of occupied area and static power consumption, this research work proposes two structures for designing and developing logic gates. The first proposed method, combining a reference resistance and parallel non-volatile elements, can generate all kinds of logical gates. The second proposed method, using only two non-volatile elements and a control current, not only can generate all kind of gates but also provide significant reliability and reduce the occupied area. The first proposed method uses more elements than the second proposed method, but its power consumption is lower. The second proposed method is applicable in such applications in which the area is more important than the power consumption, while the first proposed method is applicable in such applications in which the power consumption is more important.

5- Reconfigurable Architecture for Sorting Networks

People involved: Amin Norollah, Hakem Beitollahi, Mahdi Fazeli
2017 - 2019

“Implementing the Reconfigurable Architecture for Sorting Networks” aims at exploration of new possibilities to improve known and to develop new sorting techniques that are particularly useful for implementation using Field Programmable Gate Arrays (FPGAs). The challenge is to use reconfigurable devices to design high-performance sorters adaptable to generally unknown number of input data items. Developing low-cost, power-efficient hardware-based solutions is another important goal.

6- Energy Consumption Reduction in STT-MRAM Caches through On-Line Quality Management

People involved: Arash Salahvarzi, Amir Hosseini Monazah, Mahdi Fazeli
2017 - 2019

CMOS circuits face critical challenges like sensitivity to soft errors and static power consumption. With the change in processors production method from single-core to multi-core and the volume and number increase in on-chip memories, the static power consumption problem became a vital challenge for computer system designers. Therefore using the SRAM technology as the on-chip memory technology causes high leakage power and also unmanageable temperature increase. In order to solve this problem, in recent years applying non-volatile memories cells as the on-chip memories has attracted considerable attention. Among non-volatile technologies, STT-MRAMs technology has features like higher density, near zero leakage power, and high flexibility facing soft errors. In spite of these advantages, one of the vital challenges of STT-MRAM technologies in using in on-chip memories is dynamic power consumption during write operations. In this research, due to this fact that in many applications with approximate computing features, there is a possibility of tolerating a certain amount of error in the system output, it is tried to create a trade-off between energy consumption and output quality. This trade-off will be used in order to save consuming write energy of STT-MRAM caches. In order to control the output quality and energy consumption of write operations, a MIMO control circuit is used. One of the quality control methods is applying feedback control procedure. In this control method, Output feedback is created to compare the amount of output with a value used to reduce the error. Control problems with one controlled variable and one manipulated variable are called SISO while Control problems with multiple controlled variables and manipulated variables are called MIMO. Considering these facts, in this research using information about output quality and environmental hazards (e.g. sudden light drop) as inputs of MIMO controller and the amount of write current as its output, a trade-off between energy consumption and output quality can be occurred. The designed system in this research is used in image processing applications.

7- Efficient Design of Arithmetic Circuits for Computation platforms in Cyber physical Systems using Stochastic Computing Approach

People involved: Amir Hossein Jalilvan, Amir Hosseini, Mahdi Fazeli
2017 - 2019

The binary number representation has dominated digital logic for decades due to its compact storage requirements. However, since the number system is positional, it needs to “unpack” bits, perform computations, and repack the bits back to binary (e.g., partial products in multiplication). An alternative representation is the unary number system: we use N bits, out of which the first M are 1 and the rest are 0 to represent the value M /N (essentially base 1 numbers). Stochastic Computing refers to a field in digital logic that generates random unary streams and performs computations on such streams. The streams can be interpreted as probabilities. Such representation would allow for very simple logic to perform complex computations. For example, multiplication of two bit streams X and Y can be done using a single AND gate. Stochastic computing has been used in applications such as image processing, LDPC coding, dynamical system simulations, neural networks and signal processing. In this project, we intend to design of efficient arithmetic circuits to be employed in computation platform of Cyber Physical Systems