Publications

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Published/Accepted Journal Papers


26. V. Jamshidi, M. Fazeli, A. Patooghy, “mGate: An Universal Magnetologic Gate for Design of Energy Efficient Digital Circuits, has been accepted for publication in IEEE Transactions On Magnetics, 2017.

25. M. H. Rad, A. Patooghy, M. Fazeli, “An Efficient Programming Skeleton for Clusters of Multi-Core Processors, Springer International Journal of Parallel Computing, 2017.

23. B. Asgari, M. Fazeli, S. V. Azhari, A. Patooghy, “A Microarchitectural Approach to Enhance Lifetime and Reliability of STTRAM based Register File in Embedded Processors, IET Computer and Digital Techniques, 2016.

22. V. Moghaddas, M. Fazeli, A. Patooghy, “Reliability-Oriented Scheduling for Static-Priority Real-Time Tasks in Standby-Sparing Systems, Elsevier, Journal of Microprocessors and Microsystems, 2016.

21. M. Ranjbar, M. Fazeli, Ahmad Patooghy, ”Phase Change Memory Lifetime Enhancement via Online Data Swapping”, Elsevier, Integration, the VLSI journal, 2016.

20. S. Afsharpour, A. Patooghy, M. Fazeli, “A Performance/Energy Aware Task Migration Algorithm for Many-Core Chips”, IET Computers & Digital Techniques journal, 2016.

19. H. Farbeh, N. S. Mirzadeh, N. Farhady,S. G. Miremadi M. Fazeli, H. Asadi, ”A Cache-Assisted ScratchPad Memory for Multiple Bit Error Protection”, IEEE Transactions On VLSI Systems (IEEE-TVLSI), 2016.

18. R. Rajaei, M. Tabandeh, M. Fazeli, ”Low Cost Circuit-Level Soft Error Mitigation Techniques for Combinational Logic”, Scientia Iranica, Vol 22, No. 6, January 2016, Pages 2401-2414.

17. R. Rajaei , M. Fazeli, M. Tabandeh ”Soft Error-Tolerant Design of MRAM-based Non-Volatile Latches for Sequential Logics”, IEEE Transaction on Magnetics, Volume 51, Issue 06, 2015.

16. R. Rajaei , B. Asgari, M. Tabandeh, M. Fazeli, ”Design of Robust SRAM Cells Against Single Event Multiple Effects for Nanometer Technologies”, IEEE Transaction on Device and Material Reliability, Volume 15, Issue 03, 2015.

15. R. Rajaei, M. Tabandeh, M. Fazeli, ”Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations”, World Scientific, Journal of Circuits, Systems, and Computers, Volume 24, Issue 01, 2015.

14. M. Kamarei, M. Hajimohammadi, A. Patooghy, M. Fazeli, “An Efficient Data Aggregation Methodfor Event-Driven WSNs: A Modeling and Evaluation Approach”, To appear in Springer Wireless Personal Communications, Volume 84, No. 1, Sep. 2015, Pages 745-764.

13. R. Rajaei, M. Tabandeh, M. Fazeli, ”Soft Error Rate Estimation for Combinational Logic in Presence of Single Event Multiple Transients”,World Scientific, Journal of Circuits, Systems, and Computers, Volume 23, Issue 06, July 2014.

12. H. Sarbazi-Azad, H.R. Zarandi, M. Fazeli, ”A Parallel Clustering Algorithm on the Star Graph and Its Application”, Elsevier, Journal of Mathematical and Computer Modeling, Volume 58, Issues 3-4, August 2013, Pages 886 -897.

11. R. Rajaei, M. Tabandeh, M. Fazeli, ”Low Cost Soft Error Hardened Latch Designs for Nano-scale CMOS Technology in presence of Process Variation”, Elsevier Journal of Microelectronics Reliability, Volume 53, Issue 6, June 2013, Pages 912-924.

10. S. Yazdanshenas, M. Ranjbar Pirbasti, M. Fazeli, Ahmad Patooghy, ”Coding Last Level STT-RAM Cache For High Endurance and Low Power”, IEEE Computer Architecture Letter, Volume 13, Issue 2, May 2013, Pages 73 - 76.

9. M. Ebrahimi, S.G. Miremadi, H. Asadi, M. Fazeli,“A Low Cost Scan Chain-Based Technique to Recover Multiple Errors in TMR Systems”,, IEEE Transactions On VLSI Systems (IEEE-TVLSI), Volume 21, Issue 8, September 2012, Pages 1454-1468.

8. Z. Ghaderi, S.G. Miremadi, H. Asadi, M. Fazeli, ”HAFTA: Highly Available Fault-Tolerant Architecture to Protect SRAM-Based Reconfigurable Devices against Multiple Bit Upsets”, IEEE Transactions on Device and Material Reliability (IEEE-TDMR), Volume 13 , Issue 1, November 2012, Pages 203-212.

7. H. Asadi, M. Baradaran, M. Fazeli, S. G. Miremadi, “Efficient Algorithms to Accurately Compute Logic-Electrical-Timing Derating (LETD) of Digital Circuits”, Elsevier, Journal of Microelectronics Reliability, Volume 52, Issue 6, June 2012, Pages 1215-1226.

6. M. Fazeli, A. Namazi, S. G. Miremadi, A. Haghdoost, “Operand Width Aware Hardware Reuse: A Low Cost Approach to Resilient ALU design in Embedded Processors”,, Elsevier, Journal of Microelectronics Reliability, Volume 51, Issue 12, December 2011, Pages 2374-2387.

5. M. Fazeli, A. Namazi, S. G. Miremadi, A. Haghdoost, “Operand Width Aware Hardware Reuse: A Low Cost Approach to Resilient ALU design in Embedded Processors", Elsevier, Journal of Microelectronics Reliability, Volume 51, Issue 12, December 2011, Pages 2374-2387.

4. M. Fazeli, A. Namazi, S. G. Miremadi, “Robust Register Caching: An Energy Efficient Circuit Level Technique to Protect Register File in Embedded Processors”, IEEE Transactions On Device and Material Reliability (IEEE TDMR), Volume 10, Issue 2, June 2010, Pages 208-221.

3. Ahmad Patooghy, Seyed Ghassem Miremadi, Mahdi Fazeli, “A Low-Overhead and Reliable Switch Architecture for Network-on-Chips”,, Elsevier, Integration, the VLSI journal, Volume 43, Issue 3, June 2010, Pages 268-278.

2. M. Fazeli, S. G. Miremadi, A. Ejlali, A. Patooghy, “Low Energy Single Event Upset/Single Event Transient-Tolerant Latch for Deep SubMicron Technologies”, IET (IEE) Computers & Digital Techniques journal, Volume 3, Issue 3, May 2009, Pages 289-303.

1. M. Fazeli, R. Farivar, S. G. Miremadi, “Error Detection Enhancement in PowerPC Architecturebased Embedded Processors”,, Springer, Journal of Electronic Testing: Theory and Applications (JETTA), Volume 24, Issue 3, June 2008, Pages 21-33.

Conference Papers


1. Seyyed Mohammad Saleh Samimi, Ehsan Aerabi, Arash Nejat, M.Fazeli, David Hely, Vincent Beroulle,”High output hamming-distance achievement by a greedy logic masking approach”, IEEE East West Design and Test, EWDTS 2016.

2. S. M. Samimi, E. Arabi, Z, Kazemi, M. Fazeli, and A. Patooghy, ”Hardware Enlightening: No Where to Hide Your Hardware Trojans!”,Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, Catalunya, Spain, July 4-6, 2016.

3. V. Jamshidi, M. Fazeli, and A. Patooghy, ”A Low Hybrid MTJ/CMOS (4-2) Compressor for Fast Arithmetic Circuits”, Proceedings of the 18th CSI International Symposium on Computer Architecture Digital Systems (CADS 2015).

4. A. Hosseini, H. Farbeh, S. G. Miremadi, M. Fazeli, H. Asadi, ”FTSPM: A Fault-Tolerant ScratchPad Memory”, to appear in Proceedings of the 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2013), 24-27th June 2013, Budapest.

5. S. M. Ghafari, M. Fazeli, A. Patooghy, L. Rikhtechi, ”Bee-MMT: A load balancing method for power consumption management in cloud computing”, Proceedings of International Conference on Contemporary Computing (IC3), August 2013.

6. S. N. Ahmadian, M. Fazeli, N. Farhadi, S. G. Miremadi, ”Value Aware Low Power Register File Architecture”, Proceedings of 16th symposium on Computer Architecture and Digital Systems (CADS2012), Shiraz, Iran, May 2012 (Best Paper Award).

7. M. A. Abazari, M. Fazeli, A. Patooghy, S.G. Miremadi, ”An Efficient Technique to Tolerate MBU Faults in Register File of Embedded Processors”, Proceedings of 16th symposium on Computer Architecture and Digital Systems (CADS2012), Shiraz, Iran, May 2012.

8. H. Farbeh, M. Fazeli, F. Khsravi, S. G. Miremadi, ”Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)”, to Appear in Proceedings of Ninth European Dependable Computing Conference (EDCC 2012), Romania, May 8-11, 2012.

9. M. Fazeli, S. N. Ahmadian, S. G. Miremadi, H. Asadi, M. B. Tahoori, ”Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)”, to appear in Proceedings of the IEEEACM International Conference on Design Automation and Test In Europe (DATE’11), 14-18, March, Grenoble, France.

10. M. Fazeli, S. G. Miremadi, H. Asadi, S. N. Ahmadian, ”A Fast and Accurate Multi-Cycle Soft Error Rate Estimation Approach to Resilient Embedded Systems Design”, the 40th Annual IEEEIFIP International Conference on Dependable Systems and Networks (DSN 2010), 28 June-1 July 2010, Chicago, USA. (Student Award)

11. M. Fazeli, S. G. Miremadi, H. Asadi, M. Baradaran Tahoori, ”A Fast Analytical Approach to MultiCycle Soft Error Rate Estimation of Sequential Circuits”, the 13th Euromicro Conference on Digital System Design (DSD 2010), Sep. 1-3, 2010, Lille, France.

12. M. Fazeli, A. Namazi, S. G. Miremadi, ”An Energy Efficient Circuit Level Technique to protect Register File from MBUs and SETs in Embedded Processors”, the 39th Annual IEEEIFIP International Conference on Dependable Systems and Networks (DSN’09), June 29- July 2, Lisbon, Portugal. (Student Award)

13. M. H. Razmkhah, S. G. Miremadi, A. Ejlali, M. Fazeli, ”A Novel SETSEU Hardned Parallel I/O Port”, IEEE Circuits and Systems International Conference on Testing and Diagnosis (ICTD 2009), Apr 28-29, 2009, Chengdu, Sichuan China.

14. M. Amiri-Kamalabad, S. G. Miremadi, M. Fazeli, ”A Power Efficient Approach to Fault-Tolerant Register File Design”, The 21st International Conference on VLSI Design (VLSI-Design 2008), Heydarabad, India, 2008. (Won the Travel Fellowship)

15. N. Farazmand, M. Fazeli, S.G. Miremadi, ”CFEDC: Control Flow Error Detection and Correction for embedded systems without program interruption”, The Third International Conference on Availability, Reliability and Security (ARES 2008), March 4-7, 2008, Barcelona, Spain.

16. M. Fazeli, S.G. Miremadi, ”A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs”, the 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2008), Cambridge, MA, 2008.

17. M. Fazeli, S. A. Ahmadian, S.G. Miremadi, ”A Low Energy Soft Error-Tolerant Architecture for Register File in Embedded Processors”, 11th IEEE High Assurance Systems Engineering Symposium, (HASE 2008), Nanjing, China, 2008.

18. M. Fazeli, S. G. Miremadi, A. Patooghy, ”The Interplay of Reliability and Power Consumption in Design of SEU-Tolerant Latches for DSM Technology”, 6th IEEE East-West Design & Test Symposium, (EWDTS 2008), Lviv, Ukraine, 2008.

19. N. Amini, M. Fazeli, S. G. Miremadi, M. T. Manzuri, ”Distance-Based Segmentation: An EnergyEfficient Clustering Hierarchy for Wireless Microsensor Networks”, the Fifth Annual Conference on Communication Networks and Services Research (CNSR 2007), Fredericton, New Brunswick, Canada., May 2007.

20. N. Amini, M. Fazeli, S. G. Miremadi, ”A Hierarchical Routing Protocol for Energy Load Balancing in Wireless Sensor Networks”, the 20th IEEE Annual Canadian Conference on Electrical and Computer Engineering (CCECE 2007), Apr. 2007, Vancouver, Canada.

21. M. Fazeli, A. Patooghy, S. Gh. Miremadi, A. Ejlali, ”Feedback Redundancy: A Power-Aware SEUTolerant Latch Design in DSM Technologies”, the 37th Annual IEEEIFIP International Conference on Dependable Systems and Networks (DSN 2007), June 25-28, Edinburg, UK. (Student Award)

22. A. Patooghy, M. Fazeli, S. G. Miremadi, ” A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips”, to appear in the Proceedings of the IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC 2007), Melbourne, Victoria, Australia, Dec. 17-19, 2007.

23. A. Patooghy, M. Fazeli, S. G. Miremadi, ” Reducing Power Consumption in NoC Design with no Effect on Performance and Reliability”, to appear in the Proceedings of The 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakesh, Morocco, Dec. 11-14, 2007.

24. S.S. Miremadi, M. Fazeli, A. Patooghy, S.G. Miremadi ”Performance Evaluation of a Routing Protocol for Wireless Sensor Networks”, The third IEEE and IFIP International Conference on wireless and Optical communications Networks (WOCN 2006), Bangalore, India.

25. A. Patooghy, S. Gh. Miremadi, A. Javadtalab, M. Fazeli1, N. Farazmand, ”A solution to Single Point of Failure Using Distributed Voting”, The 2nd IEEE International Symposium on Dependable, Autonomic and Secure Computing (DASC 2006), Indiana University, Purdue University, Indianapolis, USA September 29-October 1, 2006.

26. A. Vahdatpour, M. Fazeli, S.G. Miremadi, ”Transient Error Detection in Embedded Systems Using Reconfigurable Components”, IEEE Symposium on Industrial Embedded Systems (IES’2006), Antibes Juan-Les-Pins, France, October 18-20, 2006.

27. Y. Sedaghat, S. G. Miremadi, M. Fazeli, ”A Software-Based Error Detection Technique Using Encoded Signatures”, the 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2006), Arlington, Washington DC, October 4-6, 2006.

28. A.Vahdatpour, M. Fazeli, S. G. Miremadi, ”Experimental Evaluation of Three Concurrent Error Detection Mechanisms”, the 18th IEEE International Conference on Microelectronics (ICM 2006), Dhahran, Saudi Arabia, December 16-19, 2006.

29. M. Bashiri, S. G. Miremadi, M. Fazeli, ”A Checkpointing Technique for Rollback Error Recovery in Embedded Systems ”, the 18th IEEE International Conference on Microelectronics (ICM 2006), Dhahran, Saudi Arabia, December 16-19, 2006.

30. M. Fazeli, R. Farivar, S. G. Miremadi, ”A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded systems”, the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), Monterey, California, 2005.

31. M. Fazeli, R. Farivar, S. Hessabi, S. G. Miremadi, ”A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems”, The Second Latin-American Symposium on Dependable Computing (LADC 2005), to be published by Springer-Verlag LNCS Series, Volume 3747, 2005, P.143, Salvador, Brazil, October 25-28, 2005.

32. R. Farivar, M. Fazeli, S. G. Miremadi, ”Directed Flooding: A Fault-Tolerant Routing Protocol for Wireless Sensor Networks”, International Conference on Sensor Networks (SENET 2005), Montreal, Canada, August 14, 2005.

33. R. Farivar, M. Fazeli, H. Sarbazi-Azad, ”A Cordic-Based Processor Extension for Scalar and Vector Processing”, (IPDPS-PDSEC 2005), The 6th international workshop on parallel and distributed scientific and engineering computing, Denver, Colorado, USA, April 8, 2005.

34. M. Fazeli, H. Sarbazi-Azad, R. Farivar, ”Parallel Clustering on the Star Graph”, The 6th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP 2005), to be published by Springer-Verlag LNCS Series, Melbourne, Australia, 2005.

Technical referee:

1. IEEE Transactions on Computer.

2. IEEE Transactions on VLSI.

3. IEEE Transactions on Reliability.

4. IEEE Transactions on Nuclear Science.

5. Elsevier, Microelectronics Reliability.

6. Elsevier, Microprocessors and Microsystems.

7. World Scientific, Journal of Circuits and Systems.

8. Springer, Journal of Electronic Testing, Theory and Applications