Saturday : 10-12 monday : 10-12
Instructor : Saeed Parsa email : parsa@iust.ac.ir
Teaching Assistants : Mohamad Hamzei email : hamzei@iust.ac.ir
Mehdi Sakhaei Niea email : sakhaei@iust.ac.ir
CS652002 : Parallelizing Compilers
Spring 2010
Computer Engineering Department
Iran University of Science and Technology
Menus
Course Timinng and Contacts * Course Description and Prerequisites * Main References & Handouts * Research Interests * Lectures * Essay
Saturday : 10-12 monday : 10-12
Instructor : Saeed Parsa email : parsa@iust.ac.ir
Teaching Assistants : Mohamad Hamzei email : hamzei@iust.ac.ir
Mehdi Sakhaei Niea email : sakhaei@iust.ac.ir
Description : This course deals with principles and practice of compiler optimization techniques for automatic translation of sequential to multithreaded and multiprocessing parallel code. Parallel architectures and their application in high performance computing will be discussed. The issues of dependency analysis, loop parallelization, program transformation, multithreading, scheduling, synchronization and communication will be covered.
Prerequisites : Advanced Compiler
i- References
Optimizing Compilers for High Performance Architectures, Randy Allen, Ken Kennedy, 2001.
Professional Multicore Programming (design and implementation for C++ programmes), Cammeron Hughes, Tracy Hughes, 2008
Compilers : Principles, Tools, Technique, Alfered V. Aho, 2007
Thesis
ii. Handouts
Multicores 6. Aliasing
Multicore Algorithm (power point) 7. Aliasing power points
Multicore Programming (power point)
> Compilers, Code Generation
> Optimization and Automatic Parallelization
> Instruction Reordering to Enhance Parallelism
> Automatic Translation of Sequential to Multithreaded Code
> Automatic Translation of Sequential to Distributed Code
> Loop Parallelization
|
Lecture # |
References |
Handouts |
Date |
|
| 1 | Goals and Motivations | |||
| 2 | Parallel Architectures | ref #1, pages 21..29 | Handout #1 | |
| 3 | Pipelining | ref #1, pages 21..29 | Handout #1 | |
| 4 | Vector Instructions | ref #1, pages 29..32 | Handout #1 | |
| 5 | Superscalar and VLIW Processors | ref #1, pages 32..36 | Handout #1 | |
|
6 |
Instruction Scheduling | ref #3, pages 732..736 | Handout #1 | |
|
7 -8 |
Multicore |
ref #2, pages 2..4, 15..16 | Handout #1 | |
|
9 |
Four Multicore Architectures : The AMD Opteron | ref #2, pages 21-25 | Handout #1 | |
|
10 |
The Sun UltraSparc T1 | ref #2, pages 25-28 | Handout #1 | |
|
11 |
The IBM Cell Broaedband | ref #2, pages 28-31 | Handout #1 | |
|
11 |
Intel Core 2 DUO | ref #2, pages 31-33 | Handout #1 | |
|
12 |
Dependency Theory | ref #1, pages | ||
|
13 |
Data Dependency analysis | ref #1, ref #3 | Handout #1,#5 | |
|
14 |
Aliasing | ref #3 | Handout #6, #7 | |
|
15-16 |
Control dependencies | ref #3 | Hadnout #5 | |
|
17 |
Task Graphs | ref #3 | Handout #5 | |
|
18-19 |
Task Graph pre-scheduling | |||
|
20 |
Task Graph Scheduling | |||
|
21 |
Loop Analysis |